Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices

ABSTRACT

One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a &lt;100&gt; crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacture of FETsemiconductor devices, and, more specifically, to various methods offorming low defect replacement fins for a FinFET semiconductor deviceand the resulting device structures.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storagedevices, ASIC's (application specific integrated circuits) and the like,requires the formation of a large number of circuit elements in a givenchip area according to a specified circuit layout, wherein so-calledmetal oxide field effect transistors (MOSFETs or FETs) represent oneimportant type of circuit element that substantially determinesperformance of the integrated circuits. A conventional FET is a planardevice that typically includes a source region, a drain region, achannel region that is positioned between the source region and thedrain region, and a gate electrode positioned above the channel region.Current flow through the FET is controlled by controlling the voltageapplied to the gate electrode. For example, for an NMOS device, if thereis no voltage applied to the gate electrode, then there is no currentflow through the NMOS device (ignoring undesirable leakage currents,which are relatively small). However, when an appropriate positivevoltage is applied to the gate electrode, the channel region of the NMOSdevice becomes conductive, and electrical current is permitted to flowbetween the source region and the drain region through the conductivechannel region.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the past decades. Morespecifically, the channel length of FETs has been significantlydecreased, which has resulted in improving the switching speed and inlowering operation currents and voltages of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded.

In contrast to a planar FET, there are so-called 3D devices, such as anillustrative FinFET device, which is a three-dimensional structure. Morespecifically, in a FinFET, a generally vertically positioned fin-shapedactive area is formed and a gate electrode encloses both sides and anupper surface of the fin-shaped active area to form a tri-gate structureso as to use a channel having a three-dimensional structure instead of aplanar structure. In some cases, an insulating cap layer, e.g., siliconnitride, is positioned at the top of the fin and the FinFET device onlyhas a dual-gate structure (sidewalls only). Unlike a planar FET, in aFinFET device, a channel is formed perpendicular to a surface of thesemiconducting substrate so as to reduce the physical size of thesemiconductor device. Also, in a FinFET, the junction capacitance at thedrain region of the device is greatly reduced, which tends tosignificantly reduce short channel effects. When an appropriate voltageis applied to the gate electrode of a FinFET device, the surfaces (andthe inner portion near the surface) of the fins, i.e., the verticallyoriented sidewalls and the top upper surface of the fin, form a surfaceinversion layer or a volume inversion layer that contributes to currentconduction. In a FinFET device, the “channel-width” is estimated to beabout two times (2×) the vertical fin-height plus the width of the topsurface of the fin, i.e., the fin width. Multiple fins can be formed inthe same foot-print as that of a planar transistor device. Accordingly,for a given plot space (or foot-print), FinFETs tend to be able togenerate significantly higher drive current density than planartransistor devices. Additionally, the leakage current of FinFET devicesafter the device is turned “OFF” is significantly reduced as compared tothe leakage current of planar FETs, due to the superior gateelectrostatic control of the “fin” channel on FinFET devices. In short,the 3D structure of a FinFET device is a superior MOSFET structure ascompared to that of a planar FET, especially in the 20 nm CMOStechnology node and beyond.

One process flow that is typically performed to form FinFET devicesinvolves forming a plurality of trenches in the substrate to define theareas where STI regions will be formed and to define the initialstructure of the fins, and these trenches may be formed in the substrateduring the same process operation for processing simplicity. In somecases, the trenches are desirably designed with the same pitch (forbetter resolution during lithography) and they are formed to the samedepth and width (for processing simplicity and various functionalrequirements), wherein the depth of the trenches is sufficient for theneeded fin height and deep enough to allow formation of an effective STIregion. After the trenches are formed, a layer of insulating material,such as silicon dioxide, is formed so as to overfill the trenches.Thereafter, a chemical mechanical polishing (CMP) process is performedto planarize the upper surface of the insulating material with the topof the fins (or the top of a patterned hard mask). Thereafter, anetch-back process is performed to recess the layer of insulatingmaterial between the fins and thereby expose the upper portions of thefins, which corresponds to the final fin height of the fins.

Device manufacturers are under constant pressure to produce integratedcircuit products with increased performance and lower production costsrelative to previous device generations. Thus, device designers spend agreat amount of time and effort to maximize device performance whileseeking ways to reduce manufacturing costs and improve manufacturingreliability. As it relates to 3D devices, device designers have spentmany years and employed a variety of techniques in an effort to improvethe performance capability and reliability of such devices. Devicedesigners are currently investigating using alternative semiconductormaterials, such as so-called III-V materials, to manufacture FinFETdevices which are intended to enhance the performance capabilities ofsuch devices, e.g., to enable low-voltage operation. However, theintegration of such alternative materials on silicon substrates (thedominant substrates used in the industry) is a non-trivial matter dueto, among other issues, the large difference in lattice constantsbetween such materials and silicon.

The present disclosure is directed to various methods of forming lowdefect replacement fins for a FinFET semiconductor device and theresulting device structures.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to various methods offorming low defect replacement fins for a FinFET semiconductor deviceand the resulting device structures. One illustrative device disclosedherein includes a substrate fin formed in a substrate comprised of afirst semiconductor material, wherein at least a sidewall of saidsubstrate fin is positioned substantially in a <100> crystallographicdirection of the crystalline structure of the substrate, a replacementfin structure positioned above the substrate fin, wherein thereplacement fin structure is comprised of a semiconductor material thatis different from the first semiconductor material, and a gate structurepositioned around at least a portion of the replacement fin structure.

Another illustrative device disclosed herein includes a substrate finformed in a (100) substrate comprised of a first semiconductor material,wherein a long axis of the substrate fin is positioned in a <100>crystallographic direction of the crystalline structure of the (100)substrate, a replacement fin structure positioned above the substratefin, wherein the replacement fin structure is comprised of asemiconductor material that is different from the first semiconductormaterial, and a gate structure positioned around at least a portion ofthe replacement fin structure.

Yet another illustrative device disclosed herein includes a substratefin formed in a (110) substrate comprised of a first semiconductormaterial, wherein a long axis of the substrate fin is positioned in a<110> crystallographic direction of the crystalline structure of the(110) substrate, a replacement fin structure positioned above thesubstrate fin, wherein the replacement fin structure is comprised of asemiconductor material that is different from the first semiconductormaterial, and a gate structure positioned around at least a portion ofthe replacement fin structure.

One illustrative method disclosed herein involves forming a substratefin in a substrate such that at least a sidewall of the substrate fin ispositioned substantially in a <100> crystallographic direction of thesubstrate, forming a replacement fin above the substrate fin and forminga gate structure around at least a portion of the replacement fin.

Another illustrative method disclosed herein includes obtaining a (100)silicon substrate, forming a substrate fin in the substrate such that along axis of the substrate fin is oriented at a relative angle of 45degrees relative to a <010> direction of the (100) silicon substrate,forming a replacement fin above the substrate fin, and forming a gatestructure around at least a portion of the replacement fin.

Yet another illustrative method disclosed herein includes obtaining a(110) silicon substrate, forming a substrate fin in the substrate suchthat a long axis of the substrate fin is oriented at a relative angle of90 degrees relative to a <100> direction of the (110) silicon substrate,forming a replacement fin above the substrate fin, and forming a gatestructure around at least a portion of the replacement fin.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1A depicts an illustrative example of a FinFET device with variousfeatures identified for reference purposes;

FIG. 1B depicts the orientation of the fins of an illustrative prior artFinFET device relative to the crystallographic orientation of anillustrative <100> substrate;

FIGS. 1C-1F depict various illustrative novel methods disclosed hereinfor forming low or substantially defect-free replacement fins for aFinFET semiconductor device, and various embodiments of the resultingnovel devices;

FIGS. 2A-2F depict various illustrative novel methods disclosed hereinfor forming low or substantially defect-free replacement fins for aFinFET semiconductor device employed in a CMOS application, and variousembodiments of the resulting novel devices;

FIGS. 3A-3G depict yet other illustrative novel methods disclosed hereinfor forming low or substantially defect-free replacement fins for aFinFET semiconductor device, and various embodiments of the resultingnovel devices;

FIGS. 4A-4F depict other illustrative embodiments of the novel methodsdisclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices;

FIGS. 5A-5H depict additional illustrative embodiments of the novelmethods disclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices; and

FIGS. 6A-6H depict yet other illustrative embodiments of the novelmethods disclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure is directed to various methods of forming lowdefect replacement fins for a FinFET semiconductor device and theresulting device structures. The method disclosed herein may be employedin manufacturing either an N-type device or a P-type device, and thegate structure of such devices may be formed using either so-called“gate-first” or “replacement gate” (“gate-last”) techniques. As will bereadily apparent to those skilled in the art upon a complete reading ofthe present application, the present method is applicable to a varietyof devices, including, but not limited to, logic devices, memorydevices, etc., and the methods disclosed herein may be employed to formN-type or P-type semiconductor devices. With reference to the attachedfigures, various illustrative embodiments of the methods and devicesdisclosed herein will now be described in more detail.

FIG. 1A is a perspective view of a reference FinFET semiconductor devicethat is provided for reference purposes as it relates to several basicfeatures of the FinFET device A. The FinFET device A is formed above asemiconductor substrate B. The FinFET device A includes a plurality offins C, a gate electrode D, sidewall spacers E and a gate cap layer F.The sidewalls of the fins C is denoted by the letter H. The dashed lineG depicts the long-axis or centerline of the fins C. View “X-X” in FIG.1A depicts the locations where various cross-sectional views of thedevices disclosed herein may be taken in the drawings discussed below,i.e., in a direction that is parallel to the long axis of the gateelectrode D (the gate width direction). The portions of the fins Ccovered by the gate electrode D are the channel regions of the FinFETdevice A. In a conventional process flow, the portions of the fins Cthat are positioned in the source/drain regions may be increased in sizeor even merged together (not shown in FIG. 1A) by performing one or moreepitaxial growth processes. The process of increasing the size of ormerging the fins C in the source/drain regions of the device isperformed to reduce the resistance of source/drain regions or to inducetensile or compressive stress in the channel area.

In general, the inventors have discovered that by orienting thesidewalls H and/or long axis G of the fins C of a FinFET device in acertain crystallographic orientation, the formation of replacement finstructures may be performed in such a manner that the resultingreplacement fin structures contain relatively few, if any, substantialnumber of defects. In some cases, the resulting replacement finstructures may be substantially free of defects.

FIG. 1B depicts an illustrative prior art example of how the fins of aFinFET device may be oriented relative to the crystallographicorientation of the substrate material. FIG. 1B depicts an illustrativeprior art substrate 10 having a (100) crystalline structure, wherein theuse of “( )” denotes a specific plane. Such (100) substrates are wellknown in the art and are generally commercially available from a numberof manufacturers. As is well known to those skilled in the art, thesubstrate 10 is manufactured in such a manner that the crystallineplanes within the substrate 10 are arranged in a certain orderedarrangement. For example, FIG. 1B depicts a plan view of such anillustrative substrate 10 with a surface normal “Z” in the (100)crystalline plane. As depicted therein, the (100) substrate 10 has a<010> crystallographic direction in the “Y” or vertical direction 12 (ina plan view) and a <110> crystallographic direction in the “X” orhorizontal direction 14 (in a plan view). As used herein, the “< >”designation reflects an identification of a family of equivalentdirections. The (100) substrate 10 also has a <100> crystallographicdirection in the “Z” direction i.e., in the direction into and out ofthe plan view drawing in FIG. 1B. The plan view in FIG. 1B also reflectshow illustrative fins C of a FinFET device are typically orientedrelative to various crystallographic structures of the (100) substrate10. In general, the long axis G of the fins C are typically oriented inthe <110> direction of the crystalline structure of the substrate 10.The substrate 10 includes an illustrative notch 16 that, in the depictedexample, indicates the crystallographic direction in the “Y” or verticaldirection 12 (in a plan view), i.e., the <010> crystallographicdirection. Also depicted in FIG. 1B is a cross-sectional view and a topview of an illustrative fin structure C showing the crystallineorientation of various aspects of the fin C that is formed in the (100)substrate 10. As can be seen in these views, the long axis G of the finC is positioned in the <110> crystallographic direction of thecrystalline structure of the substrate 10, while the sidewalls H of thefins C are positioned in the <110> direction of the crystallinestructure of the substrate 10.

FIG. 1C depicts one illustrative example disclosed herein wherein, incontrast to the prior art, the long axis or centerline G of the fins Care oriented in the <100> direction of a (100) substrate 10. This alsopositions the sidewall H of the fins C such that they are oriented insubstantially the same <100> direction, depending upon thecross-sectional shape of the fins C. In the depicted example, this maybe accomplished by orienting the long axis G of the fins C at a relativeangle of +/−45 degrees relative to the “Y” axis of the substrate 10toward the <011> crystalline direction of the substrate 10. Statedanother way, the long axis G of the fins is rotated +/−45 degrees, in arelative sense, to the orientation of the fins C shown in FIG. 1B. Thismay be accomplished by maintaining the notch 16 of the substrate 10 inthe depicted position and rotating the fins H such that the long axis orcenterline G of the fins is rotated +/−45 degrees relative to the Y axisof the substrate 10, shown in FIG. 1C. As can be seen, with suchrotation, the long axis G of the fins C and the upper surface of thefins H are all oriented in the <100> crystallographic orientation of thesubstrate 10, while the sidewalls H of the fins are positioned such thatthey are oriented in substantially the same <100> crystallographicorientation.

FIG. 1D depicts another illustrative example disclosed herein wherein,in contrast to the prior art, the long axis or centerline G of the finsC are oriented in the <110> direction of a (110) substrate 13, which maytend to improve mobility of electrons or holes for the FinFET devices.This arrangement also positions the sidewall H of the fins C such thatthey are positioned in a substantially <100> crystalline orientation,depending upon the cross-sectional shape of the fins C. In the depictedexample, this may be accomplished by orienting the long axis G of thefins C in a direction that is at an angle of 90 degrees relative to the<100> direction of the (110) substrate.

The inventors have discovered that, in the context of formingreplacement fin structures, by orienting the sidewalls H of thesubstrate fins such that the sidewalls of the substrate fins arepositioned substantially in a <100> direction of the crystallinestructure of the substrate, the replacement fin structures may be formedsuch that they are substantially defect-free or contain a very lownumber of defects. The degree to which the sidewalls H of the fins C arepositioned in exactly the <100> crystalline orientation depends upon thecross-sectional shape of the fins C. FIG. 1E is a TEM photograph of adevice wherein the methods disclosed herein were employed in forming thedevice. In general, the device includes a plurality of substrate fins 32and replacement fins 34 having an insulating material 36 positionedaround the fins 32/34. In the device shown in FIG. 1E, the long axis G(fin centerline that runs into and out of the drawing page) of thesubstrate fins 32 were positioned in the <100> direction of a siliconsubstrate. In the case of the tapered substrate fins 32 shown in FIG.1E, the sidewalls H of such tapered fins may be positioned slightly outof the <100> direction due to the tapered shape of the depicted fins. Ofcourse, if desired, the substrate fins 32 may be manufactured to havemore vertically oriented sidewalls or even substantially verticalsidewalls. The more vertical the sidewalls H of the substrate fins 32,the more closely they will be positioned in the <100> direction of thesubstrate. Thus, in stating that the long-axis or centerline G of thesubstrate fins 32 disclosed herein are positioned in the <100> directionof the substrate, it is intended to cover substrate fins so orientedirrespective of their cross-sectional configuration, i.e., irrespectiveof whether the substrate fins 32 are tapered or rectangular or any othershape when viewed in cross-section. In the depicted example, thereplacement fins 34 were formed of silicon/germanium and they wereformed by performing an epitaxial deposition process so as to form thereplacement fins 34 on the substrate fins 32. The conditions of theepitaxial deposition process were as follows: a temperature of 450° C.;a pressure of 10 Torr; and a duration of about 10 minutes, using silaneand germane as the precursor gases. Note the absence of any substantialdefects in the replacement fins 34 shown in FIG. 1E.

FIG. 1F is a TEM photograph of a device wherein the same methods thatwere used to form the replacement fins 34 shown in FIG. 1E wereperformed to form replacement fins 34X above the substrate fins 32. Theonly difference between the two embodiments shown in FIGS. 1E-1F isthat, in the embodiment shown in FIG. 1F, the long axis of the substratefins 32 was positioned in the <110> direction of the crystallinestructure of the substrate. This also resulted in the sidewalls of thefins shown in FIG. 1F being positioned approximately in the samecrystallographic orientation, i.e., <110>. Note the presence of thedefects 38X in the replacement fins 34X shown in FIG. 1F.

The replacement fins disclosed herein may be formed using a variety oftechniques. FIGS. 2A-2F depict various illustrative novel methodsdisclosed herein for forming low or substantially defect-freereplacement fins for FinFET semiconductor devices employed in a CMOSapplication, and various embodiments of the resulting novel devices. Inthe attached drawings, the device 100 is depicted as being formed abovea semiconductor substrate 102 comprised of a first semiconductormaterial, such as, for example, silicon, etc. The illustrative substrate102 may be a bulk semiconductor substrate, or it may be the active layerof a so-called SOI (silicon-on-insulator) substrate or a so-called SGOI(silicon/germanium on insulator) substrate. Thus, the terms “substrate,”“semiconductor substrate” or “semiconducting substrate” should beunderstood to cover all semiconductor materials and all forms of suchsemiconductor materials. The device 100 shown in FIGS. 2A-2F iscomprised of a P-type FinFET device 100P and an N-type FinFET device100N.

At the point of fabrication depicted in FIG. 2A, one or more etchingprocesses were performed on the substrate 102 through a patterned etchmask (not shown) to define a plurality of trenches 105 in the substrate102. The formation of the trenches 105 results in the formation of aplurality of substrate fins 104. Thereafter, the trenches 105 wereoverfilled with an insulating material 106 and a planarization process,e.g., a CMP process or an etch-back process, was performed to planarizethe upper surface of the layer of insulating material 106 with the uppersurface of the substrate fins 104. The aforementioned process operationsalso result in the formation of an illustrative trench isolation region108 that electrically isolates the P-type FinFET device 100P from theN-type FinFET device 100N. Of course, as will be recognized by thoseskilled in the art after a complete reading of the present application,the isolation structure 108 may be formed before or after the substratefins 104 are formed for the device 100. Importantly, in the attacheddrawings, a box with “<100>” contained therein signifies that at leastthe sidewalls of the substrate fins 104 are substantially oriented inthe <100> crystallographic direction of the substrate 102. In someembodiments, the long axis G of the fins may also be oriented in the<100> direction of the substrate 102 (for a (100) substrate) or the longaxis B may be oriented in the <110> direction of the substrate 102 (fora (110) substrate. That is, in the cross-sectional views shown herein,the sidewalls of the substrate fins 104 are substantially positioned inthe <100> crystallographic direction of the substrate 102. The layer ofinsulating material 106 discussed herein may be comprised of a varietyof different materials, such as, for example, silicon dioxide, siliconnitride, silicon oxynitride or any other dielectric material in commonuse in the semiconductor manufacturing industry, etc., or multiplelayers thereof, etc., and it may be formed by performing a variety oftechniques, e.g., chemical vapor deposition (CVD), etc.

The depth and width of the trenches 105 as well as the height and widthof the substrate fins 104 may vary depending upon the particularapplication. In one illustrative embodiment, based on current daytechnology, the width of the trenches 105 may range from about 10nm-several micrometers. In some embodiments, the substrate fins 104 mayhave a width within the range of about 5-30 nm. In the illustrativeexamples depicted in the attached figures, the trenches 105 and thesubstrate fins 104 are all of a uniform size and shape. However, suchuniformity in the size and shape of the trenches 105 and the substratefins 104 may not be required to practice at least some aspects of theinventions disclosed herein. In the example disclosed herein, thetrenches 105 are depicted as having been formed by performing ananisotropic etching process that results in the trenches 105 having aschematically depicted, generally rectangular configuration withsubstantially vertical sidewalls. In an actual real-world device, thesidewalls of the trenches 105 may be somewhat inwardly tapered, althoughthat configuration is not depicted in the attached drawings. In somecases, the trenches 105 may have a reentrant profile near the bottom ofthe trenches 105. To the extent the trenches 105 are formed byperforming a wet etching process, the trenches 105 may tend to have amore rounded configuration or non-linear configuration as compared tothe generally rectangular configuration of the trenches 105 that areformed by performing an anisotropic etching process. Thus, the size andconfiguration of the trenches 105, and the manner in which they aremade, should not be considered a limitation of the present invention.For ease of disclosure, only the substantially rectangular trenches 105will be depicted in subsequent drawings.

Next, as shown in FIG. 2B, a patterned masking layer 110 is formed thatcovers the N-type FinFET device 100N and exposes the P-type FinFETdevice 100P for further processing. The patterned masking layer 110 maybe formed using known deposition, photolithography and etchingtechniques. The patterned mask layer 110 is intended to berepresentative in nature as it could be comprised of a variety ofmaterials, such as, for example, a photoresist material, siliconnitride, silicon oxynitride, silicon dioxide, etc. Moreover, thepatterned masking layer 110 could be comprised of multiple layers ofmaterial, such as, for example, a pad oxide layer (not shown) that isformed on the substrate 102 and a silicon nitride layer (not shown) thatis formed on the pad oxide layer. Thus, the particular form andcomposition of the patterned masking layer 110 and the manner in whichit is made should not be considered a limitation of the presentlydisclosed inventions. In the case where the patterned masking layer 110is comprised of one or more hard mask layers, such layers may be formedby performing a variety of known processing techniques, such as a CVDprocess, an atomic layer deposition (ALD) process, an epitaxialdeposition process (EPI), or plasma enhanced versions of such processes,and the thickness of such a layer(s) may vary depending upon theparticular application. In one illustrative embodiment, the patternedmasking layer 110 is a hard mask layer of silicon nitride that isinitially formed by performing a CVD process to deposit a layer ofsilicon nitride and thereafter patterning the layer of silicon nitrideusing known photolithographic and etching techniques.

FIG. 2C depicts the device 100 after an etching process was performed toreduce the height of the substrate fins 104 for the P-type FinFET device100P. The etching process results in the formation of recesses 112 abovethe reduced-height substrate fins 104. In one illustrative example, therecesses 112 may a depth on the order of about 10-200 nm (which dependson the critical thickness of the material being deposited) and an aspectratio on the order of about 5:1.

FIG. 2D depicts the device 100 after a replacement fin 114 is formed ineach of the recesses 112 above the reduced height substrate fins 104 ofthe P-type FinFET device 100P. In one illustrative embodiment, thereplacement fin 114 may be comprised of a semiconductor material that isdifferent than the semiconductor material of the substrate 102. Forexample, in the case where the substrate 102 is made of silicon, thereplacement fin 114 may be made of silicon/germanium, germanium, InP,InAs, GaAs, InGaAs, InSb, InGaSb, a III-V material, etc., and it may beformed on the reduced-height substrate fins 104 by performing anepitaxial growth process. In one embodiment, the epitaxial depositionprocess is performed until such time as the replacement fin 114 issubstantially flush with the upper surface of the layer of insulatingmaterial 106.

FIG. 2E depicts the device 100 after several process operations havebeen performed. First, the patterned masking layer 110 was removed byperforming an etching process. Thereafter, another etching process wasperformed to reduce the height of the layer of insulating material 106.This latter etching process effectively defines the final fin height ofthe replacement fins 114 for the P-type FinFET device 100P and the fins104 for the N-type FinFET device 100N. The magnitude of the final finheight may vary depending upon the particular application and, in oneillustrative embodiment, may range from about 5-60 nm.

Next, as shown in FIG. 2F, schematically depicted gate structures 200are formed on the device 100 for both the P-type FinFET device 100P andthe N-type FinFET device 100N using well-known techniques. i.e.,gate-first or gate-last techniques. Of course, the materials ofconstruction used for the gate structure 200 on the P-type FinFET device100P may be different than the materials used for the gate structure 200on the N-type FinFET device 100N. In one illustrative embodiment, theschematically depicted gate structures 200 include an illustrative gateinsulation layer 200A and an illustrative gate electrode 200B. Anillustrative gate cap layer (not shown) may also be formed above theillustrative gate electrode 200B. The gate insulation layer 200A may becomprised of a variety of different materials, such as, for example,silicon dioxide, a so-called high-k (k greater than 7) insulationmaterial (where k is the relative dielectric constant), etc. Thethickness of the gate insulation layer 200A may also vary depending uponthe particular application, e.g., it may have a physical thickness ofabout 1-2 nm. Similarly, the gate electrode 200B may also be of avariety of conductive materials, such as polysilicon or amorphoussilicon, or it may be comprised of one or more metal layers that act asthe gate electrode 200B. As will be recognized by those skilled in theart after a complete reading of the present application, the gatestructures 200 depicted in the attached drawings, i.e., the gateinsulation layer 200A and the gate electrode 200B, are intended to berepresentative in nature. That is, the gate structures 200 may becomprised of a variety of different materials and they may have avariety of configurations. In one illustrative embodiment, a thermaloxidation process may be performed to form a gate insulation layer 200Acomprised of a semiconductor-based oxide material, such as germaniumoxide, silicon dioxide, a high-k layer of insulating material, HfO₂,Al₂0₃, etc. Thereafter, the gate electrode material 200B and the gatecap layer material (not shown) may be deposited above the device 100 andthe layers may be patterned using known photolithographic and etchingtechniques. In another illustrative embodiment, a conformal CVD or ALDprocess may be performed to form a gate insulation layer 200A comprisedof, for example, hafnium oxide. Thereafter, one or more metal layers(that will become the gate electrode 200B) and a gate cap layer material(not shown), e.g., silicon nitride, may be deposited above the device100.

At the point of fabrication depicted in FIG. 2F, traditionalmanufacturing techniques may be performed to complete the manufacture ofthe device 100. For example, a sidewall spacer (not shown) comprised of,for example, silicon nitride, may be formed adjacent the gate structures200. After the spacer is formed, if desired, an epitaxial growth processmay be performed to form additional semiconducting material (not shown)on the portions of the fins 114, 104 positioned outside of the spacer.Additional contacts and metallization layers may then be formed abovethe device 100 using traditional techniques. If desired, using themethods disclosed herein, the N-type FinFET device 100N may also beprovided with replacement fins that may have a different materialcomposition than the replacement fins 114 formed for the illustrativeP-type FinFET device 100P described above.

FIGS. 3A-3G depict yet other illustrative novel methods disclosed hereinfor forming low or substantially defect-free replacement fins for aFinFET semiconductor device, and various embodiments of the resultingnovel devices. FIG. 3A depicts another illustrative embodiment of thedevice 100 disclose herein at a point in fabrication wherein a patternedmask layer 120 has been formed above the substrate 102. The patternedmasking layer 120 may be comprised of the same materials as thosedescribed above for the patterned masking layer 110. FIG. 3B depicts thedevice after one or more etching processes were performed on thesubstrate 102 through a patterned mask layer 120 to define a pluralityof trenches 105 in the substrate 102. As before, the formation of thetrenches 105 results in the formation of a plurality of substrate fins104. Thereafter, as shown in FIG. 3C, the trenches 105 were overfilledwith an insulating material 106 and a planarization process, e.g., a CMPprocess or an etch-back process, was performed to planarize the uppersurface of the layer of insulating material 106 with the upper surfaceof the substrate fins 104.

FIG. 3D depicts the device 100 after an etching process was performed toremove the patterned mask layer 120 from above the substrate fins 104.This etching process results in the formation of recesses 122 thatexpose the substrate fins 104 for further processing. In oneillustrative example, the recess 122 may a depth on the order of about5-40 nm and an aspect ratio on the order of about 5:1. FIG. 3E depictsthe device 100 after another etching process was performed to reduce theheight of the exposed substrate fins 104. This etching process resultsin the formation of recesses 122A that may have a depth on the order ofabout 5-60 nm and an aspect ratio on the order of about 8:1. FIG. 3Fdepicts the device 100 after the above-described replacement fins 114are formed in the recesses 122A above the reduced height substrate fins104. FIG. 3G depicts the device 100 after several process operationshave been performed. First, another etching process was performed toreduce the height of the layer of insulating material 106. This latteretching process effectively defines the final fin height of thereplacement fins 114 for the device 100. Thereafter, the above-describedgate structure 200 was formed on the device 100. At the point offabrication depicted in FIG. 3G, traditional manufacturing techniquesmay be performed to complete the manufacture of the device 100.

FIGS. 4A-4F depict other illustrative embodiments of the novel methodsdisclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices. FIG. 4A depicts anotherillustrative embodiment of the device 100 disclosed herein at a point infabrication wherein one or more etching processes were performed on thesubstrate 102 through the patterned mask layer 120 to define a pluralityof trenches 105 in the substrate 102. As before, the formation of thetrenches 105 results in the formation of a plurality of substrate fins104. Thereafter, as shown in FIG. 4B, the trenches 105 were overfilledwith an insulating material 106 and a planarization process, e.g., a CMPprocess or an etch-back process, was performed to planarize the uppersurface of the layer of insulating material 106 with the upper surfaceof the substrate fins 104.

FIG. 4C depicts the device 100 after an etching process was performed toremove the patterned mask layer 120 from above the substrate fins 104.This etching process results in the formation of recesses 135 thatexpose the substrate fins 104 for further processing. In oneillustrative example, the recess 135 may have a depth on the order ofabout 5-60 nm and an aspect ratio on the order of about 5:1. FIG. 4Ddepicts the device 100 after the above-described replacement fins 114are formed in the recesses 135 above the substrate fins 104. FIG. 3Edepicts the device 100 after another etching process was performed toreduce the height of the layer of insulating material 106. This latteretching process effectively defines the final fin height of thereplacement fins 114 for the device 100. Thereafter, as shown in FIG.4F, the above-described gate structure 200 was formed on the device 100.At the point of fabrication depicted in FIG. 4F, traditionalmanufacturing techniques may be performed to complete the manufacture ofthe device 100.

FIGS. 5A-5H depict additional illustrative embodiments of the novelmethods disclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices. FIG. 5A depicts anotherillustrative embodiment of the device 100 disclose herein at a point infabrication wherein a fully strained layer of silicon/germanium 130(SiGe_(0.5)) was formed on the substrate 102 and after a patterned masklayer 125 was formed above the layer of silicon/germanium 130. In thisexample, the patterned mask layer 125 is comprised of a layer of silicondioxide 123 (a pad oxide) and a layer of silicon nitride 124 (a padnitride). FIG. 5B depicts the device 100 after one or more etchingprocesses were performed on the layer of silicon/germanium 130 and thesubstrate 102 through the patterned mask layer 125 to define a pluralityof trenches 105 in the substrate 102. As before, the formation of thetrenches 105 results in the formation of a plurality of substrate fins104. Thereafter, as shown in FIG. 5C, the trenches 105 were overfilledwith the insulating material 106 and a planarization process, e.g., aCMP process or an etch-back process, was performed to planarize theupper surface of the layer of insulating material 106 with the uppersurface of the patterned masking layer 125.

FIG. 5D depicts the device 100 after one or more etching processes wereperformed to remove the patterned masking layer 125 from above thesubstrate fins 104. This etching process results in the formation ofrecesses 127 that expose the layer of silicon/germanium 130 for furtherprocessing. In one illustrative example, the recesses 127 may have adepth on the order of about 5-40 nm and an aspect ratio on the order ofabout 5:1. FIG. 5E depicts the device 100 after another etching processwas performed to remove the silicon/germanium layer 130. This etchingprocess results in the formation of recesses 129 that expose thesubstrate fins 104. The recesses 129 may have a depth on the order ofabout 40-60 nm and an aspect ratio on the order of about 8:1. FIG. 5Fdepicts the device 100 after the above-described replacement fins 114are formed in the recesses 129 above the substrate fins 104. FIG. 5Gdepicts the device 100 after an etching process was performed to reducethe height of the layer of insulating material 106. This latter etchingprocess effectively defines the final fin height of the replacement fins114 for the device 100. Thereafter, as shown in FIG. 5H, theabove-described gate structure 200 was formed on the device 100. At thepoint of fabrication depicted in FIG. 5H, traditional manufacturingtechniques may be performed to complete the manufacture of the device100.

FIGS. 6A-6H depict yet other illustrative embodiments of the novelmethods disclosed herein for forming low or substantially defect-freereplacement fins for a FinFET semiconductor device, and variousembodiments of the resulting novel devices. FIG. 6A depicts anotherillustrative embodiment of the device 100 disclosed herein at a point infabrication wherein a fully strained layer of silicon/germanium 140(SiGe_(0.5)) was formed on the substrate 102 and after theabove-described patterned mask layer 125 was formed above the layer ofsilicon/germanium 140. FIG. 6B depicts the device 100 after one or moreetching processes were performed on the layer of silicon/germanium 140and the substrate 102 through the patterned mask layer 125 to define aplurality of trenches 105 in the substrate 102. As before, the formationof the trenches 105 results in the formation of a plurality of substratefins 104. Thereafter, as shown in FIG. 6C, the trenches 105 wereoverfilled with the insulating material 106 and a planarization process,e.g., a CMP process or an etch-back process, was performed to planarizethe upper surface of the layer of insulating material 106 with the uppersurface of the patterned masking layer 125.

FIG. 6D depicts the device 100 after one or more etching processes wereperformed to remove the patterned masking layer 125 from above thesilicon/germanium layer 140. This etching process results in theformation of recesses 141 that expose the layer of silicon/germanium 140for further processing. In one illustrative example, the recesses 141may have a depth on the order of about 20-40 nm and an aspect ratio onthe order of about 5:1. FIG. 6E depicts the device 100 after anotheretching process was performed to remove portions, but not all, of thesilicon/germanium layer 140, i.e., portions 140A of thesilicon/germanium layer 140 remain positioned above the substrate fins104. This etching process results in the formation of recesses 143 whichmay have a depth on the order of about 40-60 nm and an aspect ratio onthe order of about 8:1. FIG. 6F depicts the device 100 after theabove-described replacement fins 114 are formed in the recesses 143 onthe remaining portions 140A of the layer of silicon/germanium 140. Thepresence of the remaining portions 140A of the layer ofsilicon/germanium acts as a buffer that may improve the crystal qualityof the replacement fin material 114. FIG. 6G depicts the device 100after an etching process was performed to reduce the height of the layerof insulating material 106. This latter etching process effectivelydefines the final fin height of the replacement fins 114 for the device100. Thereafter, as shown in FIG. 6H, the above-described gate structure200 was formed on the device 100. At the point of fabrication depictedin FIG. 6H, traditional manufacturing techniques may be performed tocomplete the manufacture of the device 100.

As will be appreciated by those skilled in the art after a completereading of the present application, the methods disclosed herein arebroadly directed to various methods of forming substantially defect-freereplacement fins for a FinFET device. The formation of such defect-freereplacement fin structures enables the formation of devices and circuitsthat may operate at higher efficiencies as compared to prior artdevices.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

What is claimed:
 1. A device, comprising: a substrate fin formed in asubstrate comprised of a first semiconductor material having acrystalline structure, wherein at least a sidewall of said substrate finis positioned substantially in a <100> crystallographic direction ofsaid crystalline structure of said substrate; a replacement finstructure positioned above said substrate fin, said replacement finstructure comprised of a semiconductor material that is different fromsaid first semiconductor material; and a gate structure positionedaround at least a portion of said replacement fin structure.
 2. Thedevice of claim 1, wherein said substrate is a (100) substrate and saidsubstrate fin has a long axis, wherein said long axis of said substratefin is positioned in a <100> crystallographic direction of said (100)substrate.
 3. The device of claim 1, wherein said substrate is a (110)substrate and said substrate fin has a long axis, wherein said long axisof said substrate fin is positioned in a <110> crystallographicdirection of said crystalline structure of said (110) substrate.
 4. Thedevice of claim 1, wherein said substrate is one of a (100) siliconsubstrate or a (110) silicon substrate.
 5. The device of claim 1,wherein said replacement fin structure is comprised of one ofsilicon/germanium, germanium, InP, InAs, GaAs, InGaAs, InSb, InGaSb or aIII-V material.
 6. The device of claim 5, wherein said substrate iscomprised of silicon.
 7. The device of claim 1, wherein said substrateis comprised of silicon and said replacement fin structure is comprisedof silicon/germanium.
 8. A device, comprising: a substrate fin formed ina (100) substrate comprised of silicon, wherein a long axis of saidsubstrate fin is positioned in a <100> crystallographic direction ofsaid crystalline structure of said (100) substrate; a replacement finstructure positioned above said substrate fin, said replacement finstructure comprised of a semiconductor material that is different fromsaid first semiconductor material; and a gate structure positionedaround at least a portion of said replacement fin structure.
 9. Thedevice of claim 8, wherein said replacement fin structure is comprisedof one of silicon/germanium, germanium, InP, InAs, GaAs, InGaAs, InSb,InGaSb or a III-V material.
 10. A device, comprising: a substrate finformed in a (110) substrate comprised of silicon, wherein a long axis ofsaid substrate fin is positioned in a <110> crystallographic directionof said crystalline structure of said (110) substrate; a replacement finstructure positioned above said substrate fin, said replacement finstructure comprised of a semiconductor material that is different fromsaid first semiconductor material; and a gate structure positionedaround at least a portion of said replacement fin structure.
 11. Thedevice of claim 10, wherein said replacement fin structure is comprisedof one of silicon/germanium, germanium, InP, InAs, GaAs, InGaAs, InSb,InGaSb or a III-V material.
 12. A method of forming a FinFET device,comprising: forming a substrate fin in a substrate such that at least asidewall of said substrate fin is positioned substantially in a <100>crystallographic direction of said substrate; forming a replacement finabove said substrate fin; and forming a gate structure around at least aportion of said replacement fin.
 13. The method of claim 12, whereinsaid substrate is a (100) substrate and wherein said substrate fin isformed such that a long axis of said substrate fin is positioned in a<100> crystallographic direction of said (100) substrate.
 14. The methodof claim 12, wherein said substrate is a (110) substrate and whereinsaid substrate fin is formed such that a long axis of said substrate finis positioned in a <110> crystallographic direction of said (110)substrate.
 15. The method of claim 12, wherein said replacement fin iscomprised of one of silicon/germanium, germanium, InP, InAs, GaAs,InGaAs, InSb, InGaSb or a III-V material.
 16. The method of claim 12,wherein said substrate is comprised of silicon.
 17. A method of forminga FinFET device, comprising: obtaining a (100) silicon substrate;forming a substrate fin in said substrate such that a long axis of saidsubstrate fin is oriented at relative angle of 45 degrees relative to a<010> direction of said (100) silicon substrate; forming a replacementfin above said substrate fin; and forming a gate structure around atleast a portion of said replacement fin.
 18. The method of claim 17,wherein said replacement fin is comprised of one of silicon/germanium,germanium, InP, InAs, GaAs, InGaAs, InSb, InGaSb or a III-V material.19. A method of forming a FinFET device, comprising: obtaining a (110)silicon substrate; forming a substrate fin in said substrate such that along axis of said substrate fin is oriented at relative angle of 90degrees relative to a <100> direction of said (110) silicon substrate;forming a replacement fin above said substrate fin; and forming a gatestructure around at least a portion of said replacement fin.
 20. Themethod of claim 19, wherein said replacement fin is comprised of one ofsilicon/germanium, germanium, InP, InAs, GaAs, InGaAs, InSb, InGaSb or aIII-V material.